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cy93c01/02/04/08/16 1 kbit, 2 kbit, 4 kbit, 8 kbit, and 16 kbit (x8 or x16) microwire serial eeprom cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-15635 rev. *c revised february 05, 2009 features continuous voltage operation ? v cc = 1.65v to 5.5v internally organized as x8 or x16 industry standard three wire serial interface schmitt trigger, filtered inputs for noise suppression programming instructions that work on byte, word, or entire memory sequential read operation 4 mhz clock rate (5v) compatibility self timed write cycle (5 ms max) ready/busy signal during programming industrial temperature range high reliability ? endurance: 1 mill ion write cycles ? data retention: 100 years rohs compliant 8-pin soic and 8-pin tssop packages pb-free and rohs compliant functional description the cy93c01/02/04/08/16 provid es 1k, 2k, 4k, 8k, and 16k bits of serial electrically erasable and programmable read only memory (eeprom). the memory is organized as x16 when the org pin is connected to v cc and as x8 when it is tied to ground. the device is optimized for use in many industrial applications, where low power and low voltage operations are essential. the cy93c01/02/04/08/16 is availabl e in space saving 8-pin soic, and 8-pin tssop packages. the cy93c01/02/04/08/16 is enabled through the chip select pin (cs), and accessed through a three wire serial interface consisting of data input (di), data output (do), and serial clock (sk). on receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data out put pin do. the write cycle is completely self timed and no separate erase cycle is required before write. the write cycle is enabled only when the part is in the erase or write enable stat e. when cs is brought high following the initiation of a writ e cycle, the do pin outputs the ready/busy status of the part. the cy93c01/02/04/08/16 is available in a 1.65v to 5.5v version. logic block diagram cs org di v cc v ss cy93cxx do sk [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 2 of 16 pinouts figure 1. pin diagram: 8-pin soic/tssop package table 1. pin definition - 8-soic/tssop pin name 8-soic pin number 8-tssop pin number i/o type description cs 1 1 input chip select sk 2 2 input serial clock di 3 3 input serial data input do 4 4 output serial data output gnd 5 5 input ground org 6 6 input internal organization [1] nc 7 7 na no connect [2] v cc 8 8 input power supply cs org gnd 1 2 3 4 5 6 7 8 top view (not to scale) di v cc do sk nc notes 1. when the org is connected to vcc, the x16 organization is se lected. when it is connected to ground, the x8 organization is se lected. if the org pin is left unconnected and the application does not load the input beyond the capability of the internal 1meg ohm pull up, then the x16 organization i s selected. 2. the nc pin does not contribute to the normal operation of the device. the pin may be left unconnected or may be connected to vcc or gnd. direct connection of nc to gnd is recommended for lowest standby power consumption. [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 3 of 16 device operating features internal device reset to prevent inadvert ent write operations during power up, a power on reset (por) circuit is included. during power up and power down, the device must not be selected (that is, the chip select input (cs) must be driven low) until the supply voltage reac hes the operating voltage v cc . during power up (the phase during which v cc is lower than the minimum v cc , but increases continuously), the device does not respond to any instruction until v cc has reached the por threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in dc electrical characteristics on page 9). after v cc has passed the por threshold, the device is reset. before selecting the memory and is suing instructions to it, a valid and stable v cc voltage is applied. this voltage must remain stable and valid until the end of transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t wc ). during power down (the phase during which v cc decreases continuously), as soon as v cc drops from the normal operating voltage below the por threshol d voltage, the device stops responding to any inst ruction sent to it. active and standby power modes when chip select (cs) is high, the device is selected and in the active power mode. it consumes i cc , as specified in dc electrical characteristics on page 9. when chip select (cs) is low, the device is deselected. if no erase or write cycle is in progress when ch ip select goes low, the device enters the standby power mode and the power consumption drops to i sb1 . device operations the cy93c02 is accessed through a simple and versatile three wire serial communication interface. device operation is controlled by seven instructions issued by the host processor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ?1?) followed by the appropriate op-code and the desired memory address location. read the read (read) instruction contains the address code for the memory location to be read. after the instruction and address are decoded, data from the selected me mory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. note that a dummy bit (logic ?0?) precedes the 8-bit or 16-bit data output string. the cy93c02 supports sequential read operations. the device automatically increments the internal address pointer and clocks out the next memory location as long as cs is held high. in this case, the dummy bit (logic ?0?) is not clocked out between memory locations, therefore enab ling a continuous stream of data to be read. write the write (write) instruction contains 8 or 16 bits of data to be written into the specified memo ry location. the self timed programming cycle t wc starts after the last bit of data is received at serial data input pin di. t he do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 100 ns (t ce ). a logic ?0? at do indicates that programming is still in progress. a logic ?1? indicates that the memory location at the specifi ed address is written with the data pattern contained in the instruction and the part is ready for further instructio ns. a ready/busy status is not obtained if the cs is brought high after the en d of the self timed programming cycle t wc . an internal power on data protection mechanism in the cy93c02 inhibits the device when the supply is too low. erase the erase (erase) instruction prog rams all bits in the specified memory location to the logical ?1? state. the self timed erase cycle starts after the erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 100 ns (t ce ). a logic ?1? at pin do indicates that the selected memory location is erased, and the part is ready for another instruction. erase/write enable (ewen) to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instruction is carried out. note that in the ewen state, programming remains enabled until an ewds instruction is executed or v cc power is removed from the part. erase all (eral) the erase all (eral) instruct ion programs every bit in the memory array to the logic ?1? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 100 ns (t ce ). write all (wral) the write all (wral) instructi on programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 100 ns (t ce ). erase/write disable (ewds) to protect against accidental data disturbance, the erase/write disable (ewds) instruction disables all programming modes and is executed after all progra mming operations. the operation of the read instruction is in dependent of both the ewen and ewds instructions and is executed at any time. [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 4 of 16 table 2. instruction set for cy93c01 [3] instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a6?a0 a5?a0 read address an?a0 erase 1 11 a6?a0 a5?a0 clear address an?a0 write 1 01 a6?a0 a5?a0 d7?d0 d15?d0 write address an?a0 ewen 1 00 11xxxxx 11xxxx write enable ewds 1 00 00xxxxx 00xxxx write disable eral 1 00 10xxxxx 10xxxx clear all address wral 1 00 01xxxxx 01xxxx d7?d0 d15?d0 write all address table 3. instruction set for cy93c02 and cy93c04 [3] instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a8 [4] ?a0 a7 [5] ?a0 read address an?a0 erase 1 11 a8 [4] ?a0 a7 [5] ?a0 clear address an?a0 write 1 01 a8 [4] ?a0 a7 [5] ?a0 d7?d0 d15?d0 write address an?a0 ewen 1 00 11xxxxxxx 11xxxxxx write enable ewds 1 00 00xxxxxxx 00xxxxxx write disable eral 1 00 10xxxxxxx 10xxxxxx clear all address wral 1 00 01xxxxxxx 01xxxxxx d7?d0 d15?d0 write all address table 4. instruction set for cy93c08 and cy93c16 [3] instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a10 [6] ?a0 a9 [7] ?a0 read address an?a0 erase 1 11 a10 [6] ?a0 a9 [7] ?a0 clear address an?a0 write 1 01 a10 [6] ?a0 a9 [7] ?a0 d7?d0 d15?d0 write address an?a0 ewen 1 00 11xxxxxxxxx 11xxxxxxxx write enable ewds 1 00 00xxxxxxxxx 00xxxxxxxx write disable eral 1 00 10xxxxxxxxx 10xxxxxxxx clear all address wral 1 00 01xxxxxxxxx 01xxxxxxxx d7?d0 d15?d0 write all address notes 3. x = do not care bit. 4. address bit a8 is not decoded by cy93c02. 5. address bit a7 is not decoded by cy93c02. 6. address bit a10 is not decoded by cy93c08. 7. address bit a9 is not decoded by cy93c08. [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 5 of 16 ready/busy status while the write or erase cycle is underway, for a write, erase, wral or eral instructio n, the busy signal (do=0) is returned whenever chip select input (cs) is driven high. in this state, the cy93c02 ignores any da ta on the bus. when the write cycle is completed, and chip sele ct input (cs) is driven high, the ready signal (do=1) indicates that the cy93c02 is ready to receive the next instru ction. serial data ou tput (do) remains set to 1 until the chip select input (c s) is brought low or until a new start bit is decoded. common i/o operation serial data output (do) and seri al data input (di) are connected together, through a current limiting resistor, to form a common, single wire data bus. some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (a0) clashes with the first data bit on serial data output (do). clock pulse counter in a noisy environment, the number of pulses received on serial clock (sk) may be greater than the number delivered by the master (the microcontroller). this leads to a misalignment of the instruction of one or more bits, as shown in figure 8 on page 8, and may lead to the writing of erroneous data at an erroneous address. to combat this problem, the cy93c02 has an on-chip counter that counts the clock pul ses from the start bit until the falling edge of the chip select input (cs). if the number of clock pulses received is not the number expected, the write, erase, eral, or wral instructio n is aborted a nd the contents of the memory are not modified. figure 2. read instruction timing figure 3. erase enable/disable instruction timing [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 6 of 16 figure 4. write instruction timing figure 5. write all instruction timing twc tcs thzce tlzce t ce tce tlzce thzce twc [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 7 of 16 figure 6. erase instruction timing figure 7. erase all instruction timing tce tlzce twc thzce twc thzce tlzce tce [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 8 of 16 figure 8. write sequence with one clock glitch cs sk di [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 9 of 16 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .................................. ?65 c to +150 c ambient temperature with power applied ............................................. ?55 c to +125 c supply voltage on v cc relative to gnd..........?1.0v to +6.0v dc voltage applied to outputs in high-z state........................................ ?0.5v to v cc + 1.0v input voltage .......................................... ?0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential .. .................. ?1.0v to v cc + 2.0v package power dissipation capability (t a = 25c) .................................................... 1.0w surface mount lead soldering temperature (3 seconds).................. +260 c for 10 seconds output short circuit current [8] ....................................... 50 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 1.65v to 5.5v dc electrical characteristics over the operating range (v cc = 1.65v to 5.5v) parameter description test conditions min max unit v cc1 supply voltage 1.65 5.5 v i sb1 standby current v cc = 1.65v, cs = v cc 1 a i sb2 standby current v cc = 2.7v, cs = v cc 1.1 a i sb3 standby current v cc = 5.5v, cs = v cc 1.2 a i cc1 supply current (read) v cc = 5.5v at 4 mhz 2 ma i cc2 supply current (write) v cc = 5.5v 2 ma i li input leakage current v in = v cc or v ss 1 a i lo output leakage current v in = v cc or v ss 1 a v il input low voltage 1.65v < v cc < 2.7v ?0.6 [9] 0.3 v cc v 2.7v < v cc < 5.5v ?0.6 [9] 0.8 v ih input high voltage 1.65v < v cc < 5.5v 0.7 v cc v cc + 0.5 [9] v v ol output low voltage i ol = 2.1 ma, 2.7 < v cc < 5.5v 0.4 v i ol = 0.15 ma, 1.65 < v cc < 2.7v 0.2 v oh output high voltage i oh = -0.1 ma, 1.65 < v cc < 2.7v v cc ? 0.2 v i oh = -0.4 ma, 2.7 < v cc < 5.5v 2.4 capacitance in the following table, the capacitance parameters are listed. [10] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 1.65v 5pf c out output pin capacitance 5 pf thermal resistance in the following table, the thermal resistance parameters are listed. [10] parameter description test conditions 8-soic 8-tssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 120.83 119.31 c/w jc thermal resistance (junction to case) 90.31 82.77 c/w notes 8. outputs shorted for only one second. only one output shorted at a time. 9. this parameter is characterized but not tested. 10. this parameter is measured only for initial qualification and after a design or process change that could affect this parame ter. [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 10 of 16 reliability characteristics in the following table, the reliability characteristics parameters are listed. [10] parameter description test method min unit n end endurance jedec standard a117 1 million cycles t dr data rentention jedec standard a103 100 years i lth latch up jedec standard 78 100 + i cc ma figure 9. ac test loads and waveforms parameters 1.65v - 2.7v 2.7v - 5.5v unit r1 1.8k 1.8k ohm r2 1.3k 1.3k ohm c l 30 100 pf figure 10. ac input/output reference waveforms ac test inputs are driven at v iht (0.9v cc ) for a logic ?1? and v ilt (0.1v cc ) for a logic ?0?. measurement reference points for inputs and outputs are v lt (v cc /2 - 0.1v) and v ht (v cc /2 + 0.1v). input rise and fall times (10%?90%) are <3.3 ns. v cc output r2 r1 v ht reference points input v iht v ilt output v lt v ht v lt [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 11 of 16 ac switching ch aracteristics over the operating range (v cc = 1.65v?5.5v) cypress parameter alt parameter description 4 mhz 3 mhz 2 mhz 1 mhz unit min max min max min max min max f sk f sk clock frequency 4 3 2 1 mhz t cl t sklo clock pulse width low 100 130 200 400 ns t ch t skhi clock pulse width high 100 130 200 400 ns t ce t cs minimum cs low time 100 130 200 400 ns t lzce t sv output valid 100 130 200 400 ns t ces t css cs setup time 60 50 50 50 ns t ceh t csh cs hold time 0 0 0 0 ns t sd t dis data in setup time 60 50 100 100 ns t hd t dih data in hold time 60 50 100 100 ns t co2 t pd1 output delay to 1 100 130 200 400 ns t co1 t pd0 output delay to 0 100 130 200 400 ns t hzce t hz cs to data out in high impedance 60 150 150 150 ns t wc t wp write cycle time 5 5 5 5 ms t f t f input fall time 20 28 45 95 ns t r t r input rise time 20 28 45 95 ns figure 11. synchronous data timing tch tcl tsd tceh thd tces tsd tce tco1, tco2 [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 12 of 16 part numbering nomenclature ordering information density ordering code package diagram package type operating range 1 kbit cy93c01-sxi 51-85066 8-pin soic industrial cy93c01-sxit 8-pin soic (tape & reel) cy93c01-zxi 51-85093 8-pin tssop cy93c01-zxit 8-pin tssop (tape & reel) 2 kbit cy93c02-sxi 51-85066 8-pin soic industrial cy93c02-sxit 8-pin soic (tape & reel) cy93c02-zxi 51-85093 8-pin tssop cy93c02-zxit 8-pin tssop (tape & reel) 4 kbit cy93c04-sxi 51-85066 8-pin soic industrial cy93c04-sxit 8-pin soic (tape & reel) cy93c04-zxi 51-85093 8-pin tssop cy93c04-zxit 8-pin tssop (tape & reel) 8 kbit cy93c08-sxi 51-85066 8-pin soic industrial cy93c08-sxit 8-pin soic (tape & reel) cy93c08-zxi 51-85093 8-pin tssop CY93C08-ZXIT 8-pin tssop (tape & reel) 16 kbit cy93c16-sxi 51-85066 8-pin soic industrial cy93c16-sxit 8-pin soic (tape & reel) cy93c16-zxi 51-85093 8-pin tssop cy93c16-zxit 8-pin tssop (tape & reel) above table contains preliminary information. please contact your local cypress sales representative for availability of these parts. cy93 c 01 - sx i t temperature: i = industrial (C40 to 85c) option: t=tape&reel blank = std. voltage: c = 1.65v - 5.5v cypress 93 =microwire interface package: s=soic z=tssop density: 16 = 16 kb 01 = 1 kb 02 = 2 kb 04 = 4 kb 08 = 8 kb x = pb-free [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 13 of 16 package diagrams figure 12. 8-pin (150-mil) soic, 51-85066 seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 8 5 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 14 of 16 figure 13. 8-pin (4.4 mm) tssop, 51-85093 package diagrams (continued) 51-85093-*a [+] feedback
cy93c01/02/04/08/16 document #: 001-15635 rev. *c page 15 of 16 document history page document title: cy93c01/02/0 4/08/16, 1 kbit, 2 kbit, 4 kbit, 8 kbit, and 16 kbit (x8 or x16) microwire serial eeprom document number: 001-15635 revision ecn no. orig. of change submission date description of change ** 1069220 uha see ecn new data sheet *a 2522135 gvch/pyrs 06/27/08 added pb-free and rohs compliant information in features removed pdip package removed automotive temperature range changed supply voltage on v cc relative to gnd max value from 5.0v to 6.0v corrected typo of vcc max value from 5.0v to 5.5v added ac test load values for different parameters table 10: updated ac switching characteristics table 8: added thermal resistance values for 8-tssop packages table 9: changed t dr value from 20 to 100 years updated part numbering nomenclature and ordering information *b 2611873 vkn/pyrs 11/24/08 updated part numbering nomenclature updated ordering information table *c 2656511 vkn/aesa 02/09/09 changed part# from cy93c46/56/66/76/86 to cy93c01/02/04/08/16 converted from preliminary to final included v il spec of 0.8v for the v cc range between 2.7v to 5.5v updated v ih test conditions added footnote #9 updated v ol and v oh test conditions on page 10, specified v cc range for ac test load conditions on page 10, corrected ac measurement reference points from v it and v ot to v lt and v ht respectively changed v lt level from 0.3v cc to v cc /2 - 0.1v changed v ht level from 0.7v cc to v cc /2 + 0.1v [+] feedback
document #: 001-15635 rev. *c re vised february 05, 2009 page 16 of 16 all products and company names mentioned in this docum ent may be the trademarks of their respective holders. cy93c01/02/04/08/16 ? cypress semiconductor corporation, 2007-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback

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